A 3-Phase Reduced Switch Count Symmetric 17-Level Inverter Topology Supplying a Resistive Load

Duraisamy, Murali

doi:10.1590/1678-4324-2024240081

Murali Duraisamy ^**Correspondence: muraliems@gmail.com Tel.: +91-9894984592 (M.D.).

Government College of Engineering Srirangam, Tiruchirappalli, Department of Electrical and Electronics Engineering, Tamil Nadu, India

https://orcid.org/0000-0002-6890-1687

Editor-in-Chief: Alexandre Rasi Aoki

Associate Editor: Daniel Navarro Gevers

*Correspondence: muraliems@gmail.com Tel.: +91-9894984592 (M.D.).

Conflicts of Interest: The author declares no conflict of interest.

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Figure 1
Proposed 3-phase 17-level inverter topology supplying a resistive load

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Figure 2
Carrier waveform and sine wave reference for VFPWM method

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Figure 3
Carrier waveform and sine wave reference for COPWM method

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Figure 4
Carrier waveform and sine wave reference for PDPWM method

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Figure 5
3-phase line voltages generated by VFPWM strategy for the proposed inverter

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Figure 6
Harmonics present in 3-phase line voltages produced by VFPWM method

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Figure 7
3-phase line currents generated by VFPWM strategy for the proposed inverter

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Figure 8
Harmonics present in 3-phase line currents produced by VFPWM method

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Figure 9
3-phase currents generated by VFPWM strategy for the proposed inverter

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Figure 10
Harmonics present in 3-phase currents produced by VFPWM method

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Figure 11
3-phase line voltages generated by COPWM strategy for the proposed inverter

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Figure 12
Harmonics present in 3-phase line voltages produced by COPWM scheme

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Figure 13
3-phase line currents generated by COPWM strategy for the proposed inverter

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Figure 14
Harmonics present in 3-phase line currents produced by COPWM method

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Figure 15
3-phase currents generated by COPWM strategy for the proposed inverter

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Figure 16
Harmonics present in 3-phase currents produced by COPWM method

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Figure 17
3-phase line voltages produced by PDPWM strategy for the proposed inverter

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Figure 18
Harmonics present in 3-phase line voltages produced by PDPWM scheme

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Figure 19
3-phase line currents generated by PDPWM strategy for the proposed inverter

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Figure 20
Harmonics present in 3-phase line currents produced by PDPWM method

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Figure 21
3-phase currents generated by PDPWM strategy for the proposed inverter

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Figure 22
Harmonics present in 3-phase currents produced by PDPWM method

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Figure 23
Variation of Switching loss and %THD of voltage with switching frequency

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Figure 24
Variation of %THD of line and phase currents with switching frequency

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Table 1
Comparison of power switches of the proposed 17-level inverter with that of other topologies

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Table 2
Switching logic for the proposed 17-level inverter structure

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Table 3
Comparison of PDPWM, VFPWM, and COPWM strategies for the proposed 17-level inverter supplying a resistive load of 60 Ω / phase

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Table 4
Variation of Switching loss and %THD for the proposed 17-level inverter controlled by PDPWM, VFPWM, and COPWM schemes with m_a = 0.85

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(1)

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(2)

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(3)

Inverter category	No. of DC power supplies/phase	No. of power switches	No. of output voltage levels	No. of ON-state power switches
Traditional cascaded MLI [¹⁶16 Siahbalaee J, Sanaie N. Comparison of conventional and new cascaded multilevel inverter topologies based on novel indices. ISA Trans, 2022 Jan; 119:41-51.]	k	4k	2k+1	2k
Cascaded MLI proposed in [¹⁷17 Ajami A, Oskuee MRJ, Mokhberdoran A, den Bossche AV. Developed cascaded multilevel inverter topology to minimize the number of circuit devices and voltage stresses of switches. IET Power Electron, 2014 Feb; 7(2):459-66.]	k	2k+4	2k+1	k+2
Proposed 17-level cascaded MLI	k	2k+2	2k+1	k+1

Levels	S₁	S₂	S₃	S₄	S₅	S₆	S₇	S₈	S₉	S₁’	S₂’	S₃’	S₄’	S₅’	S₆’	S₇’	S₈’	S₉’	Output voltages
1	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	+8V_dc

2	1	0	1	0	1	0	1	0	0	0	1	0	1	0	1	0	1	1	+7V_dc
3	1	0	1	0	1	0	1	1	1	0	1	0	1	0	1	0	0	0	+6V_dc
4	1	0	1	0	1	0	0	0	0	0	1	0	1	0	1	1	1	1	+5V_dc
5	1	0	1	0	1	1	1	1	1	0	1	0	1	0	0	0	0	0	+4V_dc
6	1	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	+3V_dc
7	1	0	1	1	1	1	1	1	1	0	1	0	0	0	0	0	0	0	+2V_dc
8	1	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	+1V_dc
9	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	0V_dc
10	0	1	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	-1V_dc
11	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	-2V_dc
12	0	1	0	1	1	1	1	1	1	1	0	1	0	0	0	0	0	0	-3V_dc
13	0	1	0	1	0	0	0	0	0	1	0	1	0	1	1	1	1	1	-4V_dc
14	0	1	0	1	0	0	1	1	1	1	0	1	0	1	1	0	0	0	-5V_dc
15	0	1	0	1	0	0	0	0	0	1	0	1	0	1	1	1	1	1	-6V_dc
16	0	1	0	1	0	0	0	1	1	1	0	1	0	1	1	1	0	0	-7V_dc
17	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	-8V_dc

Performance factors of the proposed 17-level inverter	Sinusoidal PWM schemes
	PDPWM		VFPWM		COPWM
	m_a = 0.85	m_a = 1	m_a = 0.85	m_a = 1	m_a = 0.85	m_a = 1
%THD for output voltage	4.11	4.01	5.91	4.98	4.38	4.29
RMS output voltage (V)	438	452	441	453	460	478
Peak output voltage (V)	620	639	624	641	650	676
%THD for output phase current	4.29	3.35	6.71	5.98	7.32	6.03
%THD for output line current	3.83	3.10	4.82	4.27	4.11	3.86
RMS output phase current (A)	7.30	7.53	7.35	7.55	7.67	7.97
RMS output line current (A)	12.64	13.04	12.73	13.08	13.28	13.80
Switching loss/phase (W)	0.092	0.117	0.093	0.120	0.097	0.128

Switching frequency (f_SW) kHz	Switching loss/phase (W)			%THD of voltage			%THD of line current			%THD of phase current
Switching frequency (f_SW) kHz	PD PWM	VF PWM	CO PWM	PD PWM	VF PWM	CO PWM	PD PWM	VF PWM	CO PWM	PD PWM	VF PWM	CO PWM
2	0.092	0.093	0.097	4.11	5.91	4.38	3.83	4.82	4.11	4.29	6.71	7.32
4	0.184	0.186	0.194	4.01	5.73	4.27	3.75	4.71	4.01	4.12	6.62	7.21
6	0.276	0.278	0.290	3.83	5.24	4.12	3.62	4.62	3.89	4.01	6.53	7.02
8	0.369	0.371	0.387	3.78	4.95	3.91	3.51	4.54	3.78	3.92	6.46	6.93
10	0.460	0.464	0.484	3.63	4.83	3.83	3.44	4.41	3.64	3.84	6.37	6.85

[1] Editor-in-Chief: Alexandre Rasi Aoki

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A 3-Phase Reduced Switch Count Symmetric 17-Level Inverter Topology Supplying a Resistive Load

Abstract

HIGHLIGHTS